1. Field of the Invention
The present invention relates to the field of highly integrated chips. More particularly, the present invention concerns interrupt handling for integrated circuits containing a plurality of processors.
2. Art Background
Data processing systems in general, and microprocessors and microcontrollers in particular are commonly provided with one or more channels for sensing an interrupt. An interrupt is an event that causes a processor to make a temporary transfer of control from its current program to another program that services the event. The servicing program is referred to as the interrupt service routine (ISR), which, upon completion returns control to the previously executing program.
Interrupts may be provided upon the occurrence of various internal or external events, such as an error or fault and are the primary means by which input/output (I/O) devices obtain the services of a processor. Interrupts greatly increased the performance of a computer or control system by allowing the I/O devices direct and rapid access to the processor and by freeing the processor from the task of continually testing the status of I/O devices.
Generally, while a processor is executing the interrupt service routine for the first interrupt, the receipt of a second interrupt on the same channel by the processor may be lost. During the debug stage of the development of the processor, these situations are detected and system design is modified to prevent such an occurrance. Advances in technology have led to ever more complex integrated circuits. These advances provide for greater numbers of components on single integrated circuits. Problems arise due to these new technologies in which multiple processors are now being integrated on a single chip. In complex integrated circuits with multiple processors and peripherals there is a need for interaction between these components. Handling inter-component communication through interrupts is an efficient design solution for the above problem.
The introduction of having multiple processors on a single integrated circuit introduces a number of problems for the development of such circuits, particularly, during the debugging stage. There is a limitation to the number of signals that can be transmitted out of a given integrated circuit, dependent on the cost of the chip involved and the packaging issues of the chip. Thus, the type of interrupt errors described above may be impossible to detect. If one processor is processing an interrupt and prematurely receives another interrupt on the same channel from another processor on the integrated circuit, that interrupt may be completely lost leading to problems down the road in the execution of the system's program. Because of the limitations of the number of pins from the integrated circuit, it may not be possible that every interrupt coupling between processors can provide for outside signaling of such errors. Accordingly, to enhance the debugging of highly complex integrated circuits, it is an object of the present invention to provide the means for detecting such interrupt error conditions generated by inter-processor interrupt signaling within a single complex integrated circuit.